1. Field of the Invention
The present invention relates to a semiconductor wafer, and more specifically, to a semiconductor wafer that can avoid interlayer delamination caused by a wafer sawing process.
2. Description of the Prior Art
With the continued development of semiconductor process technology, and the miniaturization of the integrated circuit chip, many unneeded parasite capacitors are often formed in the inter-metal-dielectric (IMD) layer. Because the electrons cannot pass through the parasite capacitors until filling up the parasite capacitors, the signal transferred by the electrons is therefore delayed. That is what is called resistor-capacitor time delay effect. The resistor-capacitor time delay effect therefore becomes a limitation for raising the operation rate and the efficiency of the integrated circuit components. In order to increase the operation rate and the efficiency of the integrated circuit components, it is presently suggested that the resistances of conducting wires for the IMD layer should decrease, or the dielectric constant of the dielectric layers should decrease so as to mitigate the resistor-capacitor time delay effect. Therefore, copper with lower resistance is gradually used in place of aluminum with higher resistance to be the material of the IMD layer, and the low dielectric constant (low-k) materials are gradually used in place of the silicon oxide dielectric materials, such as fluorinated silicate glass (FSG), phosphosilicate glass (PSG), or undoped silicate glass (USG).
However, problems such as peeling or delamination are often found near the boundary between the copper and the low-k materials. After manufacturing the integrated circuit of the semiconductor wafers, the package factories should cut the wafers utilizing grinding wheels or cutters so as to perform the follow-up package processes. The mechanical internal stress is unavoidable during the mechanical cutting process, and causes cracks. Furthermore, peeling or delamination of the low-k materials is especially found when the scribe line area includes the copper and the low-k materials. This is a result of the properties of the copper and the low-k materials. The copper is fairly hard, and is more difficult to be cut in comparison with other materials in wafers. On the other hand, the low-k materials are soft or are porous structures, and the adhesion between the low-k materials and the other materials is rather poor. During the process of cutting, the grinding wheel or the cutter exerts a downward force upon the surface of the wafer. As the force is exerted on the metal pad with larger area, the whole metal pad compresses the low-k dielectric layer at its periphery. The compression leads to the peeling or the delamination of the low-k materials. As the peeling effect extends from the scribe line area to the drive circuit in the die area, it usually becomes a latent problem that damages the reliability of the final products.
Although there might be such a problem, the scribe line area cannot avoid including some metal materials with larger area, such as the metal pad. This is because the wafers should continuously be tested during manufacturing to maintain the quality of the products. At present, the wafer acceptance testing (WAT) is mostly accepted by the industry for testing wafers. It provides a plurality of test keys in the periphery area of two dies to monitor a variety of defects in the semiconductor processes. In other words, as the semiconductor processes are performed, a test component is formed in the scribe line area utilizing the same processes in the same time to simulate. The parameters of the processes are measured by utilizing a metal probe to contact the test keys, and those parameters are important indexes used to indicate the reliability of products. The mentioned test keys include metal structures in the scribe line areas. There are other metal structures in the scribe line areas, such as test components of feature dimension, alignment marks, or logos.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic top view of a traditional wafer, and FIG. 2 is a schematic cross-section view of the traditional wafer of FIG. 1. As shown in FIG. 1, a wafer 10 includes a plurality of die areas 12 arranged in an array, a plurality of first scribe line areas 14 that are essentially parallel to each other, and a plurality of second scribe line areas 16 that are essentially parallel to each other. The first scribe line areas 14 are approximately perpendicular to the second scribe line areas 16 so as to divide each die area 12 from another. Furthermore, there is a passivation layer including a low-k dielectric layer 18 or IMD layer in the surface of the wafer 10 at present. There is at least a metal test structure 20 in the first scribe line areas 14 or the second scribe line areas 16, which can be any of the test keys, test components of feature dimension, alignment marks, or logos.
As mentioned above, after manufacturing the integrated circuit in the wafer 10, the package process starts. The grinding wheel or the cutter may cut the wafer 10 along the first scribe line areas 14 and the second scribe line areas 16 so as to cut the wafer 10 into a plurality of independent die areas 12. Generally speaking, the widths of the first scribe line areas 14 and the second scribe line areas 16 can be dependent on various factors, such as the size of the wafer, the cutting method and the kind of the integrated circuit, and are usually around ten micrometers to hundreds of micrometers.
As shown in FIG. 2, after cutting the wafer 10, the peeling or delamination are easily found near the boundary between the top low-k dielectric layer 18 and the lower other materials. Especially when the cutting force is exerted on the first scribe line areas 14 to the metal structure 20 with larger area, the whole metal structure 20 compresses the low-k dielectric layer 18 in the periphery. The compression leads to the peeling or the delamination of the low-k materials. Those effects are easily transferred along the direction perpendicular to the cutting direction, and the peeling of the low-k dielectric layer 18 might extend to the inter-metal layer of the die area 12, thereby damaging the operation of the integrated circuit in the dies.